更新1:
我的第一个方法是使用xpm_cdc_handshake
宏的如下方式:
xpm_cdc_握手泛型映射(DEST_EXT_HSK => 0,——DECIMAL;0=内部握手,1=外部握手DEST_SYNC_FF => 4,——DECIMAL;INIT_SYNC_FF => 0,——DECIMAL;0=禁用模拟初始值,1=启用模拟初始值SIM_ASSERT_CHK => 0,——DECIMAL;0=禁用模拟消息,1=启用模拟消息SRC_SYNC_FF => 4,——DECIMAL;宽度=> 32——DECIMAL;port map (dest_clk => M_AXIS_ACLK,——1位输入:目标时钟。dest_req => AXIS_DestReq,——1-bit output:断言此信号表示已接收到新的dest_out数据,并已准备好由目标逻辑使用或捕获。当——DEST_EXT_HSK = 1时,一旦源握手——确认目标时钟域已经接收到传输的——数据,该信号将停止断言。当DEST_EXT_HSK = 0时,该信号在——dest_out总线有效时断言一个时钟周期。 This output is registered. dest_ack => AXIS_DestAck, -- 1-bit input: optional; required when DEST_EXT_HSK = 1 dest_out => AXIS_SyncData, -- WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain. This output is registered. src_clk => Clock, -- 1-bit input: Source clock. src_rcv => OV7670_SrcRcv, -- 1-bit output: Acknowledgement from destination logic that src_in has been -- received. This signal will be deasserted once destination handshake has fully -- completed, thus completing a full data transfer. This output is registered. src_send => OV7670_SrcSend, -- 1-bit input: Assertion of this signal allows the src_in bus to be synchronized -- to the destination clock domain. This signal should only be asserted when -- src_rcv is deasserted, indicating that the previous data transfer is complete. -- This signal should only be deasserted once src_rcv is asserted, acknowledging -- that the src_in has been received by the destination logic. src_in => OV7670_SyncData -- WIDTH-bit input: Input bus that will be synchronized to the destination clock domain. );
这个想法是设计一些逻辑来填充OV7670接收缓冲区(OV7670_SyncData
)并通过断言OV7670_SrcSend
信号。AXI4-Stream传输逻辑等待信号AXIS_DestAck
当断言该信号时,数据被同步,然后通过AXI4-Stream接口传输。
我试图实现一个OV7670相机接口与AXI4-Stream接口的数据传输。我目前的想法是实现某种FIFO或环形缓冲区来存储来自相机的数据(即一行),当FIFO满时,通过AXI4-Stream接口的数据传输开始。
但我不确定这是否是理想的方法,因为我将跨越两个时钟域(相机模块的时钟和AXI时钟),或者是否有更好的方法?