New answers taggeddigital-logic
0
If the circuit is a 7474 D - Edge triggered, unless I am wrong, you are not really wrong. From the datasheet https://www.ti.com/lit/ds/symlink/sn54ls74a-sp.pdf?ts=1629843026340&ref_url=https%253A%252F%252Fwww.google.it%252F See the description For proving this, one must use a "variable slew-rate" clock.
1
Don't dismiss a bleed resistor. It is simple, reliable, and does not depend on any other circuit components to work. A diode across the timing resistor will discharge the timing capacitor only if there is a low enough resistance through other circuit components when the power is removed. From the circuit's point of view, there are two ways power can be ...
1
You could use a small RC pair to provide a signal that stays high or low for a short time after power on: simulate this circuit – Schematic created using CircuitLab D1 solves your problem of the capacitor remaining charged after power off, but probably isn't necessary, as the input protection diodes on most CMOS device inputs would perform the same ...
1
Here's a circuit utilizing an electromagnetic relay.
2
Using the threshold of a FET as a comparator is a very questionable design practice. The threshold voltage can vary quite a bit, even for a specific FET. It’s impossible to guarantee a consistent input to output transition. The reason you don’t see a sharp transition between output-high and low also relates to the FET near-threshold behavior. As the FET gate ...
1
You can likely use an AND gate and input pulldowns on each input (i.e. a resistor from signal A to ground, and a resistor from signal B to ground). A value of 10 kOhm is probably reasonable. This causes the scenarios to become: Signal A is positive (3.3V), Signal B is positive (3.3V), Output then equals Signal B (3.3V) (and equals Signal A, and equals 3.3v ...
1
The OP seems to be asking, should I use synchronous or asynchronous reset. First, I agree with the discussion that for each clock domain, there needs to be a circuit that causes the reset distributed to the flip-flops to be synchronously deasserted. When you are using a dynamically loaded part, such as Xilinx or Intel (formerly Altera), there is little ...
3
The easy way is with a microcontroller, but that's cheating. The first "hard-core" idea that springs to mind is that if you position your sensors close enough together, less than the width of the human body, they can form quadrature, like this: You can use quadrature pairs as triggers to count up or down, by defining one of them as a "...
0
You will need two stages of multiplexers, because you have three possible choices: a is true (b is irrelevant), a is false and b is true, a and b are false. This is a possible solution:
2
What you’ve built is a JK latch. All JK latches, be they built from NAND or NOR, suffer the same problem when the clock is high and both inputs are ‘1’: they oscillate. It’s not a useful circuit. A JK flip-flop on the other hand uses two JK latch stages and is edge-triggered. This works as you would expect, toggling when both inputs are ‘1’ at clock rising ...
1
Here it is in a nutshell. Asynchronous assertion (of the reset), and synchronous de-assertion (or release) of the reset. Here's a typical application. Two different clock regions (33 MHz and 50 MHz, asynchronous wrt one another).
1
In general it's safer to use a synchronized version of the reset signal that ensures that the trailing edge of reset is synchronized with the clock, but use async reset within the block itself (like you show in your first VHDL example.) This ensures that: the block is reset even in the absence of a clock no async path timing issue The latter problem is ...
1
I solved a similar problem (need to perform an action n seconds after each reboot), as that server's BIOS initialized its built-in serial port handshaking lines in a specific way, early in the boot process. I could detect that, start a timer, and then perform the action needed (in your case, that would be pressing the Enter key). It's easy to act on a power-...
1
This sounds like a job for a dual-port circular buffer RAM. Then you leverage the optimized select logic in the RAM block instead of instancing an explicit mux.
3
Figure 1. Image source: LT1017. I want to add a circuit after comparators, so that the outputs of the comparators don't be high or low simultaneously. You don't need to. The LT1017 has a weak pull-up on the output and you can parallel as many comparators as you want. If any one of then pulls low then the common output line will be pulled low. The output ...
0
Depends on accuracy, very simple method without additional power supply is to supply Out directly from Node1. This of course requires low Node1 impedance (strong signal) to cover all Out power requirement + suppling this circuit (zeners...).
0
The main component you are looking for is a comparator. It has two inputs, and compares the voltage on each. Depending on which of the inputs is the higher voltage, it outputs high or low. There are many different comparators with different specifications, so you need to find one that fits your needs.
1
It is, indeed, common practice to use an RC circuit to hold a Reset input active for a short time after power is applied. There are reset/brownout detect ICs that will generate a reset pulse when power is applied. Flip-flops and RAM memory will generally be in a random state after power-up, unless reset.
0
这是非常有效的和有趣的问题,and not too much of surprise to you, other EEs (at least me) find that need as well. I know you are not talking about external reset nor the internal brown-out. In fact, in my faint memory, some of the FPGA supplies "reset" and "brown-out" detection that you can use it as the input and ...
0
The data pins on a RAM chip need to be "tristate". A tristate pin can be output high, output low, or high impedance (input only). Each RAM chip will need a number of state pins telling it what to do. This will vary between memories, but there will some kind of "chip select" to tell the RAM chip when you are talking to it, rather than ...
0
Memory chips (and many other parts that are used to drive a bus) have an "Output Enable" input. Their output driver circuits are only active when that input is in its Active state- otherwise, the data bus pins are inputs. Normally, only one part connected to the data bus will have its Output Enable active.
4
The data bus is used for reading and writing. Correct. Wouldn't that cause a short circuit? No. The circuits are are arranged so that only one device is asserting a signal onto the data lines at any instant. The others are all just "watching" the data lines and can read the logic level. ... the electricity would move towards the output of the ...
5
a = -a ; a = a << 1 ; Both these statements inside the combinatorial always block are not valid for synthesis at least on an FPGA, because of its unpredictable nature. It has the same signal a as input and output, i.e., you are feeding back the combinatorial output a to its own input. This cannot be simulated as well because it will trigger the ...
3
There are two possibilities for Synthesiser to explore which may depend on the tool/optimizations used: The reg o becomes a flip-flop with a 2:1 mux 'in front of it'. The two inputs of the mux will be: The input in and the output of reg o flip-flop fed back. And the mux will have rdy as select signal. The reg o becomes a flip-flop with rdy as clock enable. ...
1
In the first place, it’s not a real RTL XOR gate as the inputs A,B cannot go above 0.7V which makes for illegal Vol low levels so the RED wire is not necessary , to cause the LED to behave in XOR fashion, but if the input has series R’s after all A,B’s then the circuit give proper Vol=0 and full brightness when LED is ON and the pullup would give full 5V ...
1
Best is clearly in the eye of the beholder, and I don't know what constraints you have. Another option is serial - treat each 12 bit register as a shift register and clock the bits into a logic unit (LU), MSB first. The output is a 1 if any of the inputs are 1, and this sets the corresponding bit in the output register. Where this is different to the ...
2
The general way to do this is with something called a comparator tree. You can use a comparator tree to pick either the largest value or the smallest value. The simplest comparator tree is just a tree of magnitude comparisons between pairs of values, selecting the result with log2 levels. But each comparator is implemented as a subtractor and hence has a ...
0
Dynamic power loss in CMOS D FF’s made of TG’s and inverters may be computed as follows: Ref Cpd=17 pF, Vcc(min)= 1.65V, f(typ)= 250 MHz, Cin(typ) = 5 pF ( use for min load)
3
年代ame as every design: testing, testing, and more testing. Importantly, this must be done to a plan, rather than just using it and hoping you've covered all the cases. This could be directed tests, soak tests, formal, etc. The protocols can be very complex, so there's a good chance you won't be using all the features and signals of a given protocol. This ...
0
How to learn practical Formal Verification I recommend downloading and installing the free Yosys software and the free solvers on Ubuntu, and then follow the tutorials from Symbiotic EDA and try it out hands-on to gain experience with formal verification, because that's what I did as a senior year engineering undergraduate. The properties are written in a ...
1
It's a matter of context, and any distinction will be subtle. I know of one instance where the word "strobe" is used deliberately instead of "pulse", because the word "pulse" does not convey the same sense, or spirit, of the intended purpose. The CA3140 opamp datasheet labels one of the device's pins as "strobe". The ...
2
IEEE Std. 181-2011 "IEEE Standard for Transitions, Pulses, and Related Waveforms" does not use the term "strobe" at all. It talks about pulse waveforms: pulse waveform: A waveform whose level departs from one state, attains another state, and ultimately returns to the original state.
2
High Z is high Z, the voltage is determined by the sum of the various leakage currents and impedances to other nets, but it is not exactly well defined and varies with time, temperature, humidity, what else is happening (capacitive coupling can easily toggle a floating input), board contamination and the phase of the Jovian moons. As a practical matter all ...
2
You can handle multi-bit words in parallel or serial, or a combination of both. That's an implementation choice, that's made before the detail design is started. If you want a high throughput device, then you would choose parallel. It would be large and consume relatively high power. If you want a cheaper smaller lower power device, maybe you're building a ...
2
It is not unexpected. The datasheet guarantees that voltage is at least 2.7V when the chip is driving out 400uA into the load. Voltage will be much higher, near the supply voltage, when there is no load at all. Chips supplied with 5V are not suitable to drive inputs which tolerate only 3.3V.
4
The chip guarantees that it will output at least 2.7 Volts for a "high" output. It doesn't state anything about the maximum voltage that it can output - it may go all the way up to 5 Volts (the supply voltage). In fact, if you look at the part of the datasheet that you've circled in red, you'll see that there is no value given for the typical / ...
0
Hello Everyone and thank you for your opinions. Apparently, the problem was that I was using the Logisim for too many hours(16 hours) and constantly making new modules and running simulations so it had trouble simulating all of them. I just closed it and opened it again and the problem was gone. Thanks in advance.
1
The whole thing works fine for me in Logisim. No errors. The fact that you see "00EE" means to me that two bits are, in fact, "00". But that two other bits aren't. I can't tell you exactly where the error is, from your pictures. In general, though, I think this often occurs something you think is an input pin is actually an output pin. ...
2
It looks like your intended gate is not an AND gate, but a gate where output = (IP1 AND NOT(IP2)). It is possible to make the input transitions faster and more clean to the gate, but basically you have an indeterminate condition when both inputs are (slowly) transitioning simultaneously. Because the logic gate has no memory, its output basically depends on ...
8
There's nothing that can be done to eliminate output spikes in this circuit. The AND gate is suffering from an 'internal race condition'. This would often be referred to as a 'decoding spike', as they are most frequently met when an address word goes into something like an 74HC138 address decoder, and two address bits transition simultaneously. This isn't a ...
2
Eliminating unnecessary words we get… pump P1 runs … if U=0 only when S1=1… pump P1 runs =1 independently of S1 only if U=0 pump P1 runs if L=U=0 and S1=x P1 = U’*S1 + L’ = ((U*U)’*S1)’*L)’ shows 3 (a*b)‘s meaning 3 NAND’s
0
There's an active discussion here about the problem statement and its interpretation. I'm taking the position that: You reflected the problem statement to us, accurately. The writer could not possibly have accidentally written the part about the pump ignoring S1 when L=0 only if U=0, as well. A careful reading of the problem statement suggests that it may ...
1
Why those parentheses? When L=0, output is independent of any other input, right? So it is P1 = U'*S1+L' and it can be realized with 4 nands.
9
Unless I have made an error (very likely) I believe this can be done with 3 NAND gates. The truth table must look like this: $$\begin{smallmatrix}\begin{array}{rrr|cc} U & S1 & L & P1 & \text{comments}\\ \hline 0 & 0 & 0 & 1 &\\ 0 & 0 & 1 & 0 \\ 0 & 1 & 0 & 1 \\ 0 & 1 & 1 & 1 \\ 1 & 0 &...
0
Try starting with a complemented output to reduce the number of inversions you need: P1' = U + S1'*L If you look at the Karnaugh map for P1, you can see that it's easier to simplify P1' than P1.
3
The basic idea is correct. Less gates mean less propagation delay from the input to the output of the network. Given that 99% of the logic these day is synchronous this propagation delay is the upper limit for the clock signal. In fact one of the major techniques for speeding up logic design is pipelining: if you cut a logic network in the middle so that it ...
4
It's definitely the case that frequency can increase with simpler logic. A 3 GHz processor has 333 picoseconds to complete every operation. A few extra picoseconds of delay means lower operating frequency. Nowadays a lot of the delay is wire delay, but logic gate delay still matters. Performance doesn't necessarily increase though. The gates are there for a ...
2
The time constant of R1 and the input capacitance of the 74HC00 (and any breadboard capacitance) probably is around 5-10pF*240K = 2usec. That node will be drained to near 0V via the on-chip protection network very quickly when the power input is removed. That's probably why the designer used a relatively high value for the feedback resistor. With a fast rise ...
4
与Vcap = 0对权力和积极的反馈some RC delay, this ensures the output is always off on startup. Connecting the cap between V+ And input would have the opposite effect. Revised answer: This is a metastable condition with a race to see which input reaches the crossover threshold which is expected to be equal for all devices in the same IC....
3
I would guess that it is because the current through the 100 ohm resistor and transistor base tend to hold pin 6 at a lower voltage than pin 3 as power is coming up. This imbalance tends to be reinforced by the positive feedback of the loop, and the circuit wakes up with the LED off.
Top 50 recent answers are included